[lug] OT: Makefile oddity

[D. Stimits]

I'm using make from RH 7.1, which is the gnu make. This is supposed to
support the "include" directive inside of a Makefile, and it seems to do
this. For example, I can make macro definitions in a Makefile.whatever,
that does something like give a variable name with a path for something:
SOMETHING = /somewhere/to/look

Ok, I can later use ${SOMETHING}, even if it is just echo. But, I was
coming up with problems of dual attempts to build targets in a project
split into separate directories. So I ran with -d for debug mode. Turns
out that:
include Makefile.something


...is doing the right thing, and after that, it is calling "include" a
target! It then tries to figure out how to build Makefile.something,
looking for Makefile.c, Makefile.o, Makefile.everything_under_the_sun.
In its attempt to make the "include" directive an up-to-date target (and
it isn't a target), it is ending up doing almost everything twice!
Perhaps I need some sort of dummy rule that will force make to see
target "include" as always up-to-date? I want to include separate files
for subdirectory definitions, but I want it to only add definitions, I
do not want it to end up doing multiple evaluations of everything under
the mistaken assumption that "include Makefile.whatever" is a target and
source file. Has anyone here seen this problem before or found a way to
deal with it? 

D. Stimits, stimits at idcomm.com